The present invention relates to serial data communication receivers for data capture and clock recovery and, more particularly, to a receiver and method for minimizing capture latch offset voltage.
Serial communication receivers are used in integrated circuits, such as application specific integrated circuits (ASICs), for clock synchronization and for recovery of serial data streams from transmission channels. Clock signals and data are recovered by detecting transitions in the serial data stream and the valid data between those transitions. The time and voltage ranges over which the data is valid within each cycle in the stream is known as the data xe2x80x9ceyexe2x80x9d. In order to minimize bit errors in the recovered data, the serial data stream is preferably sampled by one or more capture latches near the center of this eye. However, the limited-bandwidth nature of a transmission channel results in distortion and closure of the data eye in both the time and voltage domains.
In addition, input-referred offset voltage induced by the capture latches can further reduce the size of the data eye. Because of random, localized process variations, each capture latch can have a slightly different input-referred offset voltage, and these voltages can differ from one receiver to the next.
A serial data communication receiver is desired that is capable of evaluating the performance of a complete transceiver system and adjusting the offset voltage of each capture latch to essentially open the eye of the incoming data stream as seen by the capture latches.
One aspect of the present invention is directed to a method of adaptively adjusting offset voltages in a serial data communications receiver. The method includes receiving an incoming serial data stream and de-serializing the serial data stream with first and second sets of data capture latches having first and second recovered data outputs, respectively. Each data capture latch comprises a respective independently adjustable input-referred offset voltage. One of the first and second sets is designated as a master set and the other as a slave set. For each of the data capture latches in the slave set, the respective offset voltage is varied over a range of offset voltage values while de-serializing the incoming serial data stream. The first and second recovered data outputs are compared while varying the offset voltage to produce an error output. Each of the respective offset voltages in the slave set is set to one of the offset voltage values based on the error output.
Another aspect of the present invention relates to a serial data communication receiver, which includes a serial data input and first and second sets of data capture latches. The first and second sets of data capture latches are coupled to the serial data input and have first and second recovered data outputs, respectively. One of the sets is designated as a master set and the other a slave set. Each data capture latch has a respective independently adjustable offset voltage. An offset adjustment control circuit varies the respective offset voltage over a range of offset voltage values for each of the data capture latches in the slave set while comparing the first and second recovered data outputs to produce an error output. The control circuit then sets each of the respective offset voltages in the slave set to one of the offset voltage values based on the error output.
Yet another aspect of the present invention relates to a serial data communication receiver, which includes a serial data input and first and second sets of data capture latches coupled to the serial data input. The first and second sets of data capture latches have first and second sets of recovered data outputs. Each data capture latch has a respective adjustable offset voltage. A comparator is coupled to the first and second recovered data outputs and has an error output. A state machine is coupled to the first and second sets of data capture latches and the comparator. The state machine is configured to execute a process in which one of the first and second sets is designated as a master set and the other as a slave set. For each of the data capture latches in the slave set, the state machine varies the respective offset voltage over a range of offset voltage values while monitoring the error output. The state machine sets each of the respective offset voltages in the slave set to one of the offset voltage values based on the monitored error output.